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| T R I Q U I N T S E M I C O N D U C T O R, I N C . The TQ8103 is a monolithic clock and data recovery (CDR) IC that receives NRZ data, extracts the high-speed clock, and presents the separated data and clock as its outputs. This device is designed specifically for SONET OC-12 and SDH STM-4 applications at 622 Mb/s. Its on-chip phase-locked loop (PLL) generates a stable 622.08 Mb/s reference based upon an external 38.88 MHz TTL reference. The PLL is based on a VCO constructed from integrated reactive components, which form a low-jitter, high-Q differential tank circuit. Both frequency- and phase-detect circuits reliably acquire and hold lock in worst-case SONET jitter conditions and scrambling patterns. The lock-detect circuitry signals when the CDR acquires frequency lock. Typical SONET/SDH system applications for the TQ8103 include: TQ8103 TELECOM PRODUCTS 622 Mb/s Clock & Data Recovery Features * Single-chip CDR circuit for 622 Mb/s data * Exceeds Bellcore and ITU jitter tolerance maps * Single-ended ECL input has loopthrough path for external 50 ohm termination to minimize stubs and reflections * Clock and data outputs are differential ECL * Provides complete high-speed OC-12/STM-4 solution when used with TQ8101 or TQ8105 Mux/Demux/Framer/PLL * External loop filter requires simple passive network * Maintains clock in absence of data * Transmission system transport cards * Switch and cross-connect line cards * ATM physical layer interfaces * Test equipment * Add/drop multiplexers Figure 1. Typical Application 1000 pF 10K SELCK XTCKI LOCK SEL VTT 50 SINO SINI DOUTP DOUTN 50 ECL data in (single-ended) * 28-pin leaded chip carrier * Can be used with a high-speed external clock VREF VTT 38.88-MHz TTL clock oscillator CKOUTP CKREF OUCHP CKOUTN V CTL 50 62 1 mF 1000 pF VTT 20K For additional information and latest specifications, see our website: www.triquint.com 1 TQ8103 Figure 2. TQ8103 Block Diagram SELCK XTCKI SEL SINO +16 SINI DQ VDD VREF VEE CKREF Frequency Detect OUCHP V CTL DOUTP DOUTN LOCK Loc k Detect Phase Detect CKOUTP Mux Charge Pump VCO CKOUTN Functional Description The TQ8103 CDR integrates separate detectors for acquiring frequency lock and maintaining precise phase lock. When the CDR is locked onto an incoming NRZ data stream, its phase-detect circuitry compares the phase of the incoming NRZ data and the phase of the generated 622.08 MHz clock. When they differ, the resulting error signal nulls the phase difference and puts the generated 622.08 MHz clock back in phase with the incoming data. In this mode, the LOCK output is high. The phase-detect circuit operates only when the incoming NRZ data transitions between states. SONET and SDH employ scrambling, which provides an average transition density of 50 percent; however, some data patterns can generate legitimate scrambled signals with a significant number of consecutive ones or zeros. The TQ8103 maintains lock over bit sequences of over 100 consecutive zeros or ones. When the input data is lost or too many bit times occur without a transition, the PLL (which generates the 622.08 MHz clock) eventually drifts. The lock-detect circuit constantly compares the generated 622.08 MHz clock (divided by 16) and the external 38.88 MHz reference. When the PLL drifts more than 2000 PPM from the reference, the LOCK output goes low. The SEL input selects between the phase-detect and frequency-detect circuits. When the PLL drifts out of lock, taking SEL low reverses the drift by switching in the frequency-detect circuit. Connecting the LOCK output directly to the SEL input should ensure that frequency lock is maintained in the absence of data. It is recommended, however, that a low-pass filter be added between LOCK and SEL to allow for orderly transitions between these circuits. Once the PLL frequency is within 500 PPM of the reference, the LOCK output returns high. As the SEL input goes high, the phase-detect circuit again maintains lock to the incoming NRZ data. The TQ8103 can also be used as a standalone 622.08 MHz frequency reference. When SEL is held low, the PLL utilizes only the frequency-detect circuit. The PLL locks onto the external 38.88 MHz reference to generate the desired 622.08 MHz output. 2 For additional information and latest specifications, see our website: www.triquint.com TQ8103 Application Information Loop Filter Design The TQ8103 requires an external loop filter. Care should be taken in the implementation of the filter. Good highfrequency design techniques should be used, with the loop filter being connected into the analog ground. The analog supply should be well filtered. Data Input Considerations The serial data input line is a high-frequency ECL signal, and should be kept in a 50 ohm controlled impedance environment. Reflections on the serial input are minimized through the use of a separate loopback termination pin, SINO. A 50 ohm chip resistor between SINO and VTT minimizes stub length for the best signal quality. Another physical design consideration is to place the TQ8103 and its companion high-speed ICs as close as possible to the optics while observing good analog design practice on supply filtering and grounding. External Frequency Reference The externally supplied 38.88 MHz CKREF input needs to have low jitter with fast rise and fall times. Typical applications will use a telecom crystal oscillator such as the Connor-Winfield S14R6-38.88. SONET requires frequency sources to be accurate to 20 ppm over temperature, voltage, and aging. The CKREF input is a reference frequency for initial frequency lock and for the lock-detect circuit, so it can tolerate accuracies of up to 100 ppm. Figure 3. External Loop Filter 20 K OUCHP VCTL 1000 pF 1 mF Jitter Tolerance Jitter tolerance describes the ability of the CDR circuit to track timing variations (jitter) in the received signal. The Bellcore and ITU specifications allow the received optical signal to contain jitter. The amount of jitter that must be tolerated is a function of the frequency content of the jitter. The CDR must tolerate many unit intervals (bit times) of low-frequency jitter, but is not asked to tolerate large amounts of jitter at higher frequency. The performance shown in the "Typical Performance Data" section shows that the TQ8103 offers a wide margin over the specification limits. Jitter tolerance is a system-level issue that is directly affected by the quality of the optics, the quality of the layout (and decoupling), and the specific implementation of the loop filter. The recommended loop filter, described above, has been chosen to provide a robust margin on jitter tolerance. For additional information and latest specifications, see our website: www.triquint.com 3 TELECOM PRODUCTS 62 TQ8103 Figure 4. TQ8103 Pinout 4 OUCHP 1 VDDA 3 VCTL 2 VEEA 26 VDD 27 VCC 28 VEE VDD VDD SINI SINO VEE 5 6 7 8 9 2 5 VCC 2 4 SEL 2 3 LOCK 2 2 SELCK 2 1 XTCKI 2 0 VEE 1 9 VCC TQ8103 CDR V REF 10 V E E 11 CK OUTN 14 D OUTN 12 D OUTP 13 CK OUTP 15 Table 1. Signal Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Signal VDDA VEEA VCTL OUCHP VDD VDD SINI SINO VEE VREF VEE DOUTN DOUTP CKOUTN Type Supply Supply Analog In Analog Out Supply Supply ECL In ECL Term Supply Analog Supply ECL Out ECL Out ECL Out Description Analog ground for VCO Analog -5V supply for VCO VCO control voltage input; connect to loop filter Charge pump output; connect to loop filter Ground (0V) Ground (0V) Serial data input Loopback of SINI for termination of serial data input; connect with 50 to VTT -5V supply Optional reference voltage for single-ended ECL input -5V supply Differential data output, complement Differential data output, true Differential clock output, complement (Continued on next page) 2 For additional information and latest specifications, see our website: www.triquint.com CKRE F 17 V D D 18 V D D 16 TQ8103 Table 1. Signal Descriptions (continued) Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Signal CKOUTP VDD CKREF VDD VCC VEE XTCKI SELCK LOCK SEL VCC VDD VCC VEE Type ECL Out Supply TTL In Supply Supply Supply ECL In TTL In TTL Out TTL In Supply Supply Supply Supply Description Differential clock output, true Ground (0V) Reference clock input for frequency detect and lock detect Ground (0V) +5V supply -5V supply External clock input; selected using SELCK External clock select: low = internal VCO, high = XTCLK Lock-detect output Detection circuit select; low = frequency-detect, high = phase-detect +5V supply Ground (0V) +5V supply -5V supply Specifications Table 2. Recommended Operating Conditions Parameter Positive supply Negative supply Termination voltage Operating ambient temperature Symbol VCC VEE VTT TA Minimum 4.5 -5.5 -1.9 0 Nominal 5 -5 -2.0 Maximum 5.5 -4.75 -2.1 85 Unit V V V C Table 3. Power Consumption Parameter Positive supply current Negative supply current Thermal impedance Note: Symbol ICC IEE JA Minimum Nominal Maximum 5 210 Unit mA mA C/W 40 These values supersede the recommended operating conditions (Table 2) unless otherwise noted. For additional information and latest specifications, see our website: www.triquint.com 5 TELECOM PRODUCTS TQ8103 Table 4. DC Characteristics--ECL I/O (1) Parameter Internal ECL reference Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage Input HIGH current Condition (2) (3) (3, 4) (5) (5) (6) Symbol VREF VIH VIL VOH VOL IIH Minimum -1100 VTT -1000 VTT Nominal -1300 Maximum -700 -1500 Unit mV mV mV mV mV A 0 10 -700 -1600 Table 5. DC Characteristics--TTL I/O (1) Parameter Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Output HIGH voltage Output LOW voltage Input capacitance VIH(MAX) VIL(MIN) IOH = 3 mA IOL = -1 mA (6) Condition Symbol VIH VIL IIH IIL VOH VOL CIN Minimum 2.0 0 -100 2.4 0 Nominal Maximum VCC 0.8 100 VCC 0.4 Unit V V A A V V pF 8 Output capacitance (6) COUT 10 pF Table 6. AC Characteristics (1) Parameter Clock to data time Data output rise/fall times Clock output rise/fall times TTL output rise/fall times Acquire time Condition Figure 5 (7) (7) (8) (9) Symbol tO t R , tF t R , tF t R , tF Minimum 100 Nominal Maximum 350 350 300 Unit ps ps ps ns ms 5 3 Notes (Tables 4, 5, and 6): 1. Applies over recommended operating range 2. Single-ended inputs, VEE = -5V 3. VREF = -1300 mV 4. VTT = -2.0V 5. RLOAD = 50 ohms to VTT = -2.0V 6. Not tested; consistent with VOH and VOL tests 7. 50 ohm load, 20% to 80% levels 8. 20 pF load, 0.8V to 2.0V 9. With recommended loop filter Figure 5. Clock-to-Data Timing CKOUT DOUT tO 2 For additional information and latest specifications, see our website: www.triquint.com TQ8103 Table 7. Absolute Maximum Ratings Parameter Positive supply Negative supply Output voltage Output current Input voltage Input current Output voltage Output current Input voltage Input current Junction temperature Storage temperature Power dissipation Symbol VCC VEE VO IO VI II VO IO VI II TJ TS PD Minimum Nominal 0 -7 VEE - 0.5 -- VEE - 0.5 -1 -0.5 -0.5 -1 -55 -65 Maximum 7 0 +0.5 40 +0.5 1 VCC + 0.5 20 VCC + 0.5 1 +150 +175 2 Unit V TELECOM PRODUCTS V V mA V mA V mA V mA C C W ECL ECL ECL ECL TTL TTL TTL TTL Notes: * If the device is subjected to the listed conditions, its reliability may be impaired. * Beyond the listed conditions, the safety of the device cannot be guaranteed. For additional information and latest specifications, see our website: www.triquint.com 7 TQ8103 Typical Performance Data Figure 6. Jitter Tolerance 4 3.5 Jitter Tolerance, unit intervals TQ8103 Jitter Tolerance Bellcore Limit 3 2.5 2 1.5 1 0.5 0 10 100 Frequency (KHz) 1000 10000 Figure 7. Output Eye Diagram with extracted clock Table 8. Typical Performance Data Waveforms PRBS data pattern RMS jitter Peak-to-peak jitter 2012 2-23 7.855 ps 55 ps 2 For additional information and latest specifications, see our website: www.triquint.com TQ8103 Mechanical Specifications Figure 8. TQ8103 Package Dimensions .490 .005 .045 X 45 .445 .005 .040 MIN. 1 .410 .015 8 22 .445 .005 .490 .005 .028 .018 15 .015 X 45 (3 PLCS) .104 .005 .125 VENT PLUG .050 TYP . NON-A CCUM. .060 Ordering Information TQ8103-Q ETF-8103 622 Mb/s Clock & Data Recovery IC in 28-pin MQuad Package Evaluation Board Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: applications@tqs.com The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997 For additional information and latest specifications, see our website: www.triquint.com 9 TELECOM PRODUCTS .172 .005 |
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